Receiver and packet formatter for decoding an atsc dtv signal

ABSTRACT

A packet formatter for use in a television receiver capable of receiving a dual bitstream signal comprising a standard stream compatible with the Advanced Television Systems Committee (ATSC) standard and a robust stream. The packet formatter comprises: 1) a first processing block capable of receiving the dual bitstream signal and removing therefrom header bits and parity bits associated with the robust stream to thereby produce a first output signal; and 2) a second processing block capable of receiving the first output signal and removing therefrom duplicate bits associated with the robust stream to thereby produce a second output signal that is output from a data path output of the packet formatter.

The present invention relates generally to television receivers and, inparticular, to a receiver architecture and packet formatter for decodinga dual bit-stream ATSC Digital Television (DTV) signal.

The Advanced Television Systems Committee (ATSC) has adopted 8 VestigialSideband (8-VSB) as the standard for terrestrial broadcasting of DigitalTelevision (DTV) signals. In order to improve system performance and tosatisfy the demand of broadcasters for flexibility in terms of carryingmultiple bit-streams, Philips Research USA has proposed a transmissionsystem for embedding a robust bit-stream in the existing standardbit-stream in a backward compatible manner. The system is disclosed inU.S. patent application Ser. No. [Docket No. 703910], entitled“Apparatus and Method for Generating Robust ATSC 8-VSB Bit-Streams,” andU.S. patent application Ser. No. 09/781,486, entitled “System and Methodfor Sending Low Rate Data on a Packet Basis in an 8-VSB Standard DataPacket Stream.” The disclosures of application Ser. Nos. [Docket No.703910] and 09/781,486 are hereby incorporated by reference into thepresent application as if fully set for herein. The new transmissionsystem has the ability to trade off data rates for robustness, theoption to include a backward-compatible parity byte generator, theoption to choose from different modulation schemes, and the like.

FIG. 1 is a block diagram illustrating conventional eight levelvestigial sideband (8-VSB) receiver 100 according to an exemplaryembodiment of the prior art. Conventional 8-VSB receiver 100 comprisesantenna 105, tuner 110, filter and synchronization detector block 115,NTSC rejection filter 120, equalizer 125, phase tracker 130, andsynchronization and timing block 135. Receiver 100 also comprises aforward error correction section 140. FEC section 140 comprises trellisdecoder 150, data de-interleaver 155, Reed-Solomon (RS) decoder 160, anddata de-randomizer 165. Receivers from different manufacturers vary fromthis basic architecture, especially in the carrier recovery section(i.e., tuner 110), the timing recovery section (i.e., synchronizationand timing block 135), and the equalizer section. However, the forwarderror correction (FEC) section of receiver 100 is typical of mostreceivers.

Tuner 110 receives an incoming RF signal from antenna 105. Tuner 110down-converts the received RF signal to an intermediate frequency (IF)signal. Filter and synchronization detector block 115 filters the IFsignal and converts the IF signal to digital form. At the output offilter and synchronization detector block 115, the detected signalcomprises a stream of data symbols, where each symbol signifies a levelin an eight (8) level constellation. Synchronization and timing block135 generates synchronization and timing signals from the symbol stream.NTSC rejection filter 120 filters the symbol stream. The filtered outputfrom NTSC rejection filter 120 undergoes equalization in equalizer 125and phase tracking in phase tracker 130. Trellis decoder 150 trellisdecodes the recovered encoded data symbols from phase tracker 130 anddata de-interleaver 155 de-interleaves the decoded data bytes. RSdecoder 160 decodes the de-interleaved data bytes. Finally, the outputof RS decoder 160 is de-randomized by data de-randomizer 165 to producethe MPEG compatible data packets that were originally transmitted toconventional 8-VSB receiver 100.

Trellis decoder 150 comprises 12 trellis decoder blocks in parallel,where each trellis decoder sees every 12^(th) data symbol. The 12trellis decoder blocks receive symbols from phase tracker 130 and decodethe data symbols to get back the pre-coded and the convolutional encodedbits. The decoded bits are then grouped into bytes and passed on to datade-interleaver 155. Data de-interleaver 155 comprises a convolutionalde-interleaver circuit that performs the inverse operation of thetransmitter convolutional interleaver. The output of convolutional datade-interleaver 155 is sent to the (207 bytes, 187 bytes) t=10 RS decoder160. RS decoder 160 is capable of correcting a maximum of 10 byte errorsper packet. RS decoder 160 then passes the corrected data packets(without the parity bytes) to data de-randomizer 165. De-randomizer 165reverses the operation performed by the data randomizer in thetransmitter, thereby recovering the transport stream packets.De-randomizer 165 is synchronized with the field synchronizationsignals.

The new flexible transmission system proposed by Philips Research USA iscapable of simultaneously transmitting two bit-streams in the samephysical channel. The new transmitter includes some signal parameters,such as MODE, TR, NRP, NRS, and the like, that can be modified by thebroadcaster. MODE defines the type of modulation used for the newstream, TR defines the additional coding rate used, NRP defines thenumber of new stream packets per field, and NRS defines the presence ofa backward-compatible parity byte generator (BCPBG). Any receiverdesigned to decode the signals transmitted by a new ATSC transmittermust have a mechanism to identify and track the symbols and bytes ofdifferent bit-streams. Such a receiver should also be capable ofdecoding the two bit-streams optimally within the implementationconstraints. These requirements mean that the conventional architectureof receiver 100 in FIG. 1 must be modified to include new control andsignal processing blocks.

To meet the requirements of the new dual bit-stream transmitters, thepresent invention introduces a new ATSC receiver that includes a newreceiver packet formatter, a new robust data de-interleaver, and a newdata de-randomizer. A receiver according to the principles of thepresent invention may be implemented in hardware, as well as software(i.e., digital signal processor embodiment). The dual stream VSBreceiver can decode a standard bit-stream and a robust streamtransmitted by a new ATSC transmitter. The dual stream VSB receiver alsocan decode a conventional ATSC signal transmitted by an existingtransmitter. The new receiver also takes advantage of the pseudo 2-VSBbit-stream to improve the performance of the 8-VSB bit-stream.

To address the above-discussed deficiencies of the prior art, it is aprimary object of the present invention to provide a packet formatterfor use in a television receiver capable of receiving a dual bitstreamsignal comprising a standard stream compatible with the AdvancedTelevision Systems Committee (ATSC) standard and a robust stream.According to an advantageous embodiment of the present invention, thepacket formatter comprises: 1) a first processing block capable ofreceiving the dual bitstream signal and removing therefrom header bitsand parity bits associated with the robust stream to thereby produce afirst output signal; and 2) a second processing block capable ofreceiving the first output signal and removing therefrom duplicate bitsassociated with the robust stream to thereby produce a second outputsignal that is output from a data path output of the packet formatter.

According to one embodiment of the present invention, the packetformatter passes bytes associated with the standard stream to the datapath output of the packet formatter after delaying the standard streambytes by a predetermined delay time.

According to another embodiment of the present invention, the packetformatter comprises a third processing block capable of determining thelocations of the parity bits in the robust stream.

According to still another embodiment of the present invention, thethird processing block is further capable of determining the locationsof the header bits in the robust stream.

According to yet another embodiment of the present invention, the thirdprocessing block comprises a look-up table.

According to a further embodiment of the present invention, the packetformatter generates and output packet identification information used bysubsequent processing blocks following the packet formatter.

It is another primary object of the present invention to provide a datade-randomizer for use in a television receiver capable of receiving adual bitstream signal comprising a standard stream compatible with theAdvanced Television Systems Committee (ATSC) standard and a robuststream. According to an advantageous embodiment of the presentinvention, the data de-randomizer comprises: 1) a standard de-randomizercapable of de-randomizing bytes associated with the standard stream; and2) a robust de-randomizer capable of de-randomizing bytes associatedwith the robust stream.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, itmay be advantageous to set forth definitions of certain words or phrasesused throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterm “controller” means any device, system or part thereof that controlsat least one operation, whether such a device is implemented inhardware, firmware, software or some combination of at least two of thesame. It should be noted that the functionality associated with anyparticular controller may be centralized or distributed, whether locallyor remotely. Definitions for certain words and phrases are providedthroughout this patent document, and those of ordinary skill in the artwill understand that such definitions apply in many, if not most,instances to prior as well as future uses of such defined words andphrases.

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, wherein likenumbers designate like objects, and in which:

FIG. 1 illustrates a conventional eight level vestigial sideband (8-VSB)receiver according to an exemplary embodiment of the prior art;

FIG. 2 illustrates the forward error connection (FEC) block of an eightlevel vestigial sideband (8-VSB) receiver according to an exemplaryembodiment of the present invention;

FIG. 3 is a block diagram illustrating in greater detail the generatetd_hd_sd block of the 8-VSB receiver according to an exemplaryembodiment of the present invention;

FIG. 4A is a block diagram illustrating in greater detail the packetformatter block of the 8-VSB receiver according to an exemplaryembodiment of the present invention;

FIG. 4B is a block diagram illustrating the operation (for oneparticular set of parameters) of the remove header and parity placeholder processing block in the packet formatter block according to anexemplary embodiment of the present invention;

FIG. 4C is a block diagram illustrating the operation of the removeduplicate bits processing block in the packet formatter block accordingto an exemplary embodiment of the present invention;

FIG. 5 is a logic diagram illustrating in greater detail the robustde-interleaver block of the 8-VSB receiver according to an exemplaryembodiment of the present invention;

FIG. 6 is a block diagram illustrating in greater detail the robustde-interleaver block of the 8-VSB receiver according to an exemplaryembodiment of the present invention; and

FIG. 7 illustrates in greater detail the de-randomizer block of the8-VSB receiver according to an exemplary embodiment of the presentinvention.

FIGS. 2 through 7, discussed below, and the various embodiments used todescribe the principles of the present invention in this patent documentare by way of illustration only and should not be construed in any wayto limit the scope of the invention. Those skilled in the art willunderstand that the principles of the present invention may beimplemented in any suitably arranged ATSC digital television receiver.

FIG. 2 is a block diagram illustrating selected portions of the forwarderror connection (FEC) section of eight level vestigial sideband (8-VSB)receiver 200 according to an exemplary embodiment of the presentinvention. The receiver front-end of receiver 200 is similar to thereceiver front-end of conventional receiver 100 in FIG. 1 (i.e., tuner110, filter and synchronization detector 115, NTSC rejection filter 120,equalizer 125, etc.). The only receiver front-end component shown inFIG. 2 is equalizer 210. For the sake of brevity and clarity, adescription of the rest of the front-end of the new 8-VSB receiver 200is not repeated here.

The forward error correction (FEC) section of receiver 200 comprisestrellis decoder 220, convolutional de-interleaver 230, packet formatter240, robust de-interleaver 250, Reed-Solomon (RS) decoder 260, andde-randomizer 270. The FEC section of receiver 200 further comprisessynchronization detector 272, generate td_hd_sd block 274, decodesynchronization header block 276, and generate ps_hd_sd block 278. TheFEC section of receiver 200 is capable of decoding signals transmittedby the new dual bit-stream VSB transmitter. As FIG. 2 illustrates, mostof the functional blocks in the signal processing path (or data path)are derived from the existing architecture of prior art receiver 100.The functionality of these blocks is enhanced to support the decoding ofthe two bit-streams. In addition to this, new signal processing blocksare added to process robust bit-stream packets.

The blocks in the control path are used to identify and track thesymbols and bytes that belong to different bit-streams. The blocks inthe control path are synchronization detector 272, generate td_hd_sdblock 274, decode synchronization header block 276, and generateps_hd_sd block 278. The blocks in the data path are trellis decoder 220,convolutional de-interleaver 230, packet formatter 240, robustde-interleaver 250, RS decoder 260 and de-randomizer 270. In FIG. 2,control signal paths 281-290 are shown as dotted lines and data paths291-297 are shown as solid lines. It is noted that equalizer 210,trellis decoder 220, and synchronization detector 272 operate on thesymbol clock, while the rest of the functional blocks in the data pathoperate on the byte clock. Synchronization detector 272 detects thefield synchronization signal and the segment synchronization signal. Allof the functional blocks in FIG. 2 are synchronized with the fieldsynchronization signal and the segment synchronization signal.

Decode synchronization header block 276 decodes the fieldsynchronization header information to extract the MODE, TR, NRS, and NRPparameters, which are output on control signal path 283. The decodedMODE, TR, NRP and NRS parameters are sent over control path signal 283to generate td_hd_sd block 274, trellis decoder 220, and generate ps_hdsd block 278. Decode synchronization header block 276 also determines ifthe received signal is transmitted by a new dual bit-stream ATSCtransmitter or a prior art transmitter.

FIG. 3 illustrates generate td_hd_sd block 274 of 8-VSB receiver 200according to an exemplary embodiment of the present invention. Generatetd_hd_sd block 274 comprises generate hd_sd_in block 310, convolutionalbit interleaver 315, and trellis interleaver 320. The functionality ofthese blocks is very similar to the corresponding blocks in thetransmitter. Generate td_hd_sd block 274 generates the td_hd_sd controlsignal on control signal path 281 for use by trellis decoder 220 andequalizer 210. The td_hd_sd control signal changes per symbol and isused to determine if the symbol at equalizer 210 and trellis decoder 220belongs to a standard stream or a new dual bit-stream. The td_hd_sdcontrol signal is synchronized with the field synchronization signal.

Generate hd_sd_in block 310 generates control information at packetlevel based on the MODE, TR, NRP and NRS parameters received on controlsignal path 283. The output of generate hd_sd_in block 310 is set toLogic 1 if the packet belongs to the new stream (NS) and is equal toLogic 0 if the packet belongs to a standard stream (SS). Generatehd_sd_in block 310 only starts when back-end lock is obtained and issynchronized with the field synchronization and the segmentsynchronization signals.

Convolutional bit interleaver 315 is similar to the convolutional byteinterleaver specified in the standard, except that the memory element isone bit instead of one byte. Convolutional bit interleaver 315 tracksbytes belonging to the two bit-streams through the convolutionalinterleaver in the data path. Convolutional bit interleaver 315interleaves the output of generate hd_sd_in block 310.

Trellis interleaver 320 implements the 12-symbol trellis interleavercircuit. The output of trellis interleaver is the td_hd_sd controlsignal on control signal path 281. The td_hd-sd control signal isgreater than 0 (i.e., 1, 2 or 3) when trellis decoder 220 input symbol(or equalizer 210 output symbol) belongs to a new stream (NS). Thetd_hd-sd control signal is equal to 0 when trellis decoder 220 inputsymbol belongs to a standard stream (SS). Equalizer 210 uses thetd_hd-sd control signal to get a better estimate of the symbol andtrellis decoder 220 uses the td_hd-sd control signal in metriccalculations. The output of generate td_hd_sd block 274 should beperfectly synchronized with the input to trellis decoder 220. The outputshould be generated by the time the first valid data symbol appears atthe input of trellis decoder 220.

Generate ps_hd_sd block 278 generates the ps_hd_sd control signal oncontrol signal path 285. Generate ps_hd_sd block 278 is similar togenerate hd_sd_in block 310 except that generate ps_hd_sd block 278 issynchronized with convolutionade-interleaver 230 output synchronizationsignal. Generate ps_hd_sd block 278 is reset on each field based on thede-interleaver 230 start/reset signal. The ps_hd_sd control signal isused to control the processing of the blocks following the convolutionalde-interleaver 230 in the data path.

Trellis decoder 220 is based on the Viterbi algorithm and is used todecode the convolutional encoded symbols. Trellis decoder 220 receivesthe equalized symbols from equalizer 210, receives the MODE, TR, NRP andNRS control signals on control signal path 283 from decodesynchronization header block 276, and receives the td_hd_sd controlsignal from generate td_hd_sd block 274 on control signal path 281.Trellis decoder 220 uses soft decision decoding to decode the receivedsymbols. The trellis decoder of conventional (prior art) receiver 100has to decode only the bits corresponding to the rate-⅔ trellis encodedsymbols. In new dual bit-stream receiver 200, trellis decoder 220 mustbe able to decode the standard bit-stream bits, as well as the robustbit-stream bits. The robust bit-stream bits are encoded using differentencoding schemes, such as Pseudo 2-VSB, E-VSB, and the like. Most of theperformance gain for the robust stream is obtained through the robustcoding. Trellis decoder 220 decodes all bit-streams without any loss inperformance.

As in a conventional receiver, trellis decoder 220 comprises 12 trellisdecoder circuits in parallel, where each decoder sees every 12^(th)symbol. Trellis decoder 220 uses the td_hd_sd control signal todetermine if the received symbol is encoded as a standard stream symbolor as a robust stream symbol. Trellis decoder 220 uses different metriccalculation methods for different modes of operation. The decoded bitsare assembled into bytes and are then passed on to convolutionalde-interleaver 230.

Convolutional de-interleaver 230 performs the same function as aconventional de-interleaver in a prior art receiver. Convolutionalde-interleaver 230 receives data and control signals from trellisdecoder 220 via data path 293 and control signal path 286. Convolutionalde-interleaver 230 de-interleaves the standard stream (SS) bytes and thenew stream (NS) bytes using the same algorithm (i.e., convolutionalde-interleaver 230 does not differentiate between SS bytes and NSbytes). The de-interleaved data and the delayed control signals are thensent to packet formatter 240 via data path 294 and control signal path287, respectively. The control signals from convolutional de-interleaver230 are also sent to generate ps_hd_sd block 278 via control signal path284.

FIG. 4A is a block diagram illustrating in greater detail packetformatter 240 of 8-VSB receiver 200 according to an exemplary embodimentof the present invention. Packet formatter 240 comprises remove headerand parity place holder (PPH) processing block 410, PPHcalculator/look-up table (LUT) processing block 420, and removeduplicate bits processing block 430. Packet formatter 240 in receiver200 performs the inverse operation of the transmitter packet formatter(T×PF). In the ATSC transmitter, the transmitter packet formatterduplicates the bits of the robust packets, so that the information bitsare always placed in the LSB positions (6, 4, 2, 0) for the trellisencoder in the transmitter. Because of this transformation, each robustinformation packet is converted into two robust packets. In order tosatisfy backward-compatibility requirements (i.e., when NRS=1), the T×PFalso inserts 23 additional bytes in each new robust packet after theduplication step.

Receiver packet formatter 240 (R×PF) is placed after convolutionalde-interleaver 230 in the data path. TABLE 1 shows the functionality ofpacket formatter 240 for different combinations of MODE, TR and NRSparameters. New stream (NS) refers to either the robust bit-stream (whenMODE=2 or 3) or the embedded bit-stream (when MODE=1). Packet formatter240 only reformats bytes and packets belonging to the new stream (NS).The bytes belonging to the standard stream (SS) are just passed throughwith an appropriate delay. Packet formatter 240 also generates controlinformation for packet identification to be used by the subsequentprocessing blocks in the data path. The following description discussesprocessing for MODE=2 or 3. The new stream is made up of robustinformation (RI) packets and robust NULL (RN) packets. The ps_hd_sdcontrol signal determines if the bytes belong to the standard stream(SS) or to the new stream (NS). TABLE 1 Packer Formatter 240Functionality for Different Parameter Combinations MODE TR NRSFunctionality 0 0/1 0/1 Pass through 1 0 0 Convert 2 NS packets to 1robust information packet and 1 embedded information packet 0 1 Convert9 NS packets to 4 robust information packets, 4 embedded informationpackets and 1 NULL packet 2, 3 0 0 Convert 2 NS packets to 1 robustinformation packets and 1 NULL packet 0 1 Convert 9 NS packets to 4robust information packets and 5 NULL packets 1 0 Convert 4 NS packetsto 1 robust information packet and 3 NULL packets 1 1 Convert 9 NSpackets to 2 robust information packets and 7 NULL packets

When NRS=1, PPH calculator/LUT processing block 420 identifies thelocation of the additional parity bytes and header bytes inserted by thebackward-compatible parity byte generator (BCPBG). Remove header and PPHprocessing block 410 then removes the additional parity bytes and headerbytes. Remove duplicate bits processing block 430 then removes theduplicate bits from all the robust bytes.

FIG. 4B is a block diagram illustrating an exemplary operation of removeheader and parity place holder (PPH) processing block 410 in packetformatter 240 according to one exemplary embodiment of the presentinvention. Remove header and PPH processing block 410 removes parityplace holder (PPH) bytes and header (HDR) bytes from robust packet 441,robust packet 442, and part of robust packet 443 to produce packet 444and packet 445. Then, remove duplicate bits processing block 430 removesduplicate bits from packet 444 and packet 445 to produce robustinformation (RI) packet 446.

FIG. 4B shows the operation for NRP=162 (1100). Remove header and PPHprocessing block 410 is only active when NRS=1. Remove header and PPHprocessing block 410 uses information from PPH calculator/LUT processingblock 420 to determine if the incoming byte belongs to the data stream,to the additional header bytes, or to the BCPBG parity bytes. The first3 bytes of an incoming robust packet are the additional header bytes andare therefore removed from the packet. The parity place holder (PPH)location number is dependent on the NS packet position in the frame. ThePPH location number is compared with the incoming byte position withinthe packet. If the location number and the incoming byte position match,then the byte is dropped and the comparison moves on to the nextposition in the look-up table [LUT]. The LUT contains the PPH locationnumbers for different packet positions in the frame.

FIG. 4C is a block diagram illustrating the operation of removeduplicate bits processing block 430 in packet formatter 240 according toan exemplary embodiment of the present invention. Remove duplicate bitsprocessing block 430 is invoked in all cases when MODE=2 or 3. Afterremove header and PPH processing block 410 removes the additional 3header bytes and 20 parity bytes, the remaining bytes of packet 444(Packet 0) and packet 445 (Packet 1) are sent to remove duplicate bitsprocessing block 430. FIG. 4C shows the operation of remove duplicatebits processing block 430 for an exemplary case with TR=0. In thisexample, remove duplicate bits processing block 430 processes Packet 0and Packet 1 by combining pairs of bytes (e.g., Byte 0 ₀ and Byte 0 ₁)to form one byte (Byte 0) by selecting the LSBs (bits 6, 4, 2, 0) fromeach pair of byte.

Next, remove duplicate bits processing block 430 groups the bytes thusformed (e.g., Byte 0) into a 207 byte robust information (RI) packet andsends each RI packet, along with the NULL packets, to the followingblocks in the data-path. The NULL packets are made up of zero-valuedbytes. The NULL packet headers are later modified by de-randomizer 270so that they appear as NULL packets to the MPEG decoder. The order ofthe robust information packets and the NULL packets at the output ofpacket formatter 240 is shown in TABLE 2 for the case of NRS=1. Thispattern repeats every 9 NS packets (i.e. 4 RI+5 NULL packets). TABLE 2Classification of Robust Packets Based on Packet Number When NRS = 1Robust packet # mod 9 Packet type at Packet type at (rob_pac_cnt)Transmitter PF input Receiver PF output 0 Robust Info (RI) Place Holder(NULL) 1 Place Holder (NULL) Place Holder (NULL) 2 Robust Info (RI)Robust Info (RI) 3 Place Holder (NULL) Place Holder (NULL) 4 Robust Info(RI) Robust Info (RI) 5 Place Holder (NULL) Place Holder (NULL) 6 RobustInfo (RI) Robust Info (RI) 7 Place Holder (NULL) Place Holder (NULL) 8Place Holder (NULL) Robust Info (RI)

The receiver packet formatter 240 processing is more clearly describedby the following example. Consider a case with the following parameters:MODE=3, TR=0, NRS=1and NRP=54. TABLE 3 shows the ordering of thepackets, at the input (I/P) to the transmitter packet formatter (T×PF),at the input (I/P) to receiver packet formatter 240 (R×PF), and at theoutput (O/P) of R×PF for this parameter set. In Table 3, “RI” indicatesrobust information packets, “RN” indicates NULL packets, “Std” indicatesstandard stream packets, and “Rob” indicates encoded robust packets.Packet 0 corresponds to the first packet after the field synchronizationsignal. TABLE 3 Exemplary Packet Ordering for Selected Parameters atDifferent Points in Transmitter and Receiver # I/P to TxPF I/P to RxPFO/P of RxPF 0 RI 0 Rob 0 RN 1 Std 0 Std 0 Std 0 2 Std 1 Std 1 Std 1 3Std 2 Std 2 Std 2 4 RN Rob 1 RN 5 Std 3 Std 3 Std 3 6 Std 4 Std 4 Std 47 Std 5 Std 5 Std 5 8 RI 1 Rob 2 RI 0 9 Std 6 Std 6 Std 6 10 Std 7 Std 7Std 7 11 Std 8 Std 8 Std 8 12 RN Rob 3 RN 13 Std 9 Std 9 Std 9 14 Std 10Std 10 Std 10 15 Std 11 Std 11 Std 11 16 RI 2 Rob 4 RI 1 17 Std 12 Std12 Std 12 18 Std 13 Std 13 Std 13 19 Std 14 Std 14 Std 14 20 RN Rob 5 RN21 Std 15 Std 15 Std 15 22 Std 16 Std 16 Std 16 23 Std 17 Std 17 Std 1724 RI 3 Rob 6 RI 2 25 Std 18 Std 18 Std 18 26 Std 19 Std 19 Std 19 27Std 20 Std 20 Std 20 28 RN Rob 7 RN 29 Std 21 Std 21 Std 21 30 Std 22Std 22 Std 22 31 Std 23 Std 23 Std 23 32 RN Rob 8 RI 3 33 Std 24 Std 24Std 24 34 Std 25 Std 25 Std 25 35 Std 26 Std 26 Std 26 36 RI 4 Rob 9 RN37 Std 27 Std 27 Std 27 38 Std 28 Std 28 Std 28 --- --- --- --- 71 Std54 Std 54 Std 54 72 RI 8 Rob 18 RN 72 Std 55 Std 55 Std 55 74 Std 56 Std56 Std 56 75 Std 57 Std 57 Std 57 76 RN Rob 19 RN --- --- --- --- 204 RI23 Rob 51 RI 22 205 Std 153 Std 153 Std 153 206 Std 154 Std 154 Std 154207 Std 155 Std 155 Std 155 208 RN Rob 52 RN 209 Std 156 Std 156 Std 156210 Std 157 Std 157 Std 157 211 Std 158 Std 158 Std 158 212 RN Rob 53 RI23 213 Std 159 Std 159 Std 159 214 Std 160 Std 160 Std 160 215 Std 161Std 161 Std 161 216 Std 162 Std 162 Std 162 217 Std 163 Std 163 Std 163218 Std 164 Std 164 Std 164 219 Std 165 Std 165 Std 165 220 Std 166 Std166 Std 166 221 Std 167 Std 167 Std 167 222 Std 168 Std 168 Std 168 223Std 169 Std 169 Std 169 --- --- --- --- 308 Std 254 Std 254 Std 254 309Std 255 Std 255 Std 255 310 Std 256 Std 256 Std 256 311 Std 257 Std 257Std 257

NRP=54 indicates that there are 54*4/9=24 RI packets and 54−24=30 RNpackets in each field at the input to the T×PF. The T×PF formats the RIand RN packets to form the robust packets (referred to as “Rob”). Thereceiver receives these packets in the order shown in column “I/P toR×PF”. Since the information in RI 0 is spread into Rob 0, Rob 1 and Rob2 packets, receiver packet formatter 240 must wait until it receives Rob2 packet before it can recreate RI 0. Therefore, during the duration ofRob0 and Rob 1, packet formatter 240 sends out NULL (all zero) packets.Once receiver 200 gets the Rob 8 packet, receiver 200 can recreate RI3.This completes the process of converting 9 robust packets to 4 RIpackets. Packet formatter 240 then starts processing the next group ofrobust packets. Column “O/P of R×PF” shows the order of the robustinformation packets at the output of packet formatter 240.

Receiver packet formatter 240 introduces a fixed delay of 2 robustpackets in the robust information packets. The delay is variable interms of the number of packets, since the inter-robust packet spacing isnot fixed. TABLE 4 shows the delay for different NRP values. Thisdisplay will affect the de-randomizer down the data path. The followingsections describe a modified de-randomization scheme, which takes intoaccount the delay introduced by the R×PF. TABLE 4 Delay Introduced byPacket Formatter 240 For Different NRP Values NRP Inter-robust packetspacing Delay (packets) 0000 0 0 0001 4 8 0010 4 8 0011 4 8 0100 4 80101 4 8 0110 4 8 0111 4 8 1000 4 8 1001 2 4 1010 2 4 1011 2 4 1100 1 21101 1 2 1110 1 2 1111 1 2

FIG. 5 is a logic diagram illustrating in greater detail robustde-interleaver 250 of 8-VSB receiver 200 according to an exemplaryembodiment of the present invention. Robust de-interleaver 250 is a newsignal processing block that processes only the bytes belonging to therobust stream. Robust de-interleaver 250 is similar in structure to astandard de-interleaver. Robust de-interleaver 250 comprises aconvolutional de-interleaver with the number of rows equal to 69 and thesize of the block equal to 3. In the example shown in FIG. 5, M=3, B=69and N=207. Robust de-interleaver 250 receives data and control signalsfrom packet formatter 240 via data path 295 and control signal path 288,respectively. Robust de-interleaver 250 only processes bytes belongingto robust information (RL) packets and delays (processing delay)appropriately all other bytes (belonging to the NULL packets and theSS). If the signal is encoded without a robust interleaver at thetransmitter, then an option is provided to operate robust de-interleaver250 in by-pass mode. Robust de-interleaver 250 introduces a variableamount of initial delay for the robust stream. This delay is dependenton the NRP parameter. Robust de-interleaver 250 uses the fieldsynchronization and packet formatter 240 output control signals tosynchronize to the first data byte of first RI packet in the field. Asthe robust interleaving is on top of the standard interleaving, therobust bit-stream has high error resilience to burst errors.

FIG. 6 is a block diagram illustrating in greater detail the robustde-interleaver 250 of 8-VSB receiver 250 according to an exemplaryembodiment of the present invention. Robust de-interleaver 250 comprisesde-multiplexer (De-MUX) 610, memory 620, multiplexer (MUX) 630, latencylook-up table (LUT) 640, and generate start signal processing block 650.Robust de-interleaver 250 receives the data and the control signals frompacket formatter 240 and sends out de-interleaved data and controlsignals to RS decoder 260. Robust de-interleaver 250 uses the ps_hd_sdcontrol signal (control signal path 285) and the rob_pac_cnt controlsignal (control signal path 288) to de-multiplex the incoming data. Theps_hd_sd control signal determines if the incoming byte belongs to thenew stream (NS) or to the standard stream (SS). The rob_pac_cnt controlsignal determines if the byte belongs to the RI packet or to the RNpacket within the NS. Robust de-interleaver 250 sends the incoming databyte to memory 620 if the control signals indicate that the byte belongsto RI packet. Otherwise, the data is passed through unaltered.Multiplexer 630 uses the ps_hd_sd and rob_pac_cnt control signals tomultiplex the RI packets, Std packets and RN packets. Multiplexer 630reads data from memory 620 if the ps_hd_sd and rob_pac_cnt controlsignals indicate that the byte belongs to RI packet. Otherwise,multiplexer 630 reads data from the output of de-multiplexer 610.

Robust de-interleaver 250 must generate a signal to indicate thelocation of the first data byte of the first RI packet in a field. Thelocation of the first RI data byte in a field depends on two factors:the robust interleaver size and the parameters TR, NRS and NRP. Therobust interleaver size is fixed, resulting in fixed delay in terms ofRI packets. This delay (in bytes) can be calculated as:rd_size=3*((n−1)*n/2)*2,where n=69. The delay can also be expressed in 207-byte packets as 68 RIpackets.

The packet insertion mechanism in the new ATSC transmitter introduces avariable amount of delay between two successive RI packets depending onthe TR, NRS and NRP parameters. Therefore, robust de-interleaver 250also introduces a variable amount of delay between the fieldsynchronization and the first RI data byte in terms of the actual numberof packets (i.e. RI+Std+RN combined). This delay can be calculated byusing the following algorithm:

Step 1: Let m be the inter-robust packet spacing (see TABLE 4)corresponding to the TR, NRS and NRP parameters. The value of m is 1, 2,or 4.

Step 2: Let NRI be the number of robust information packets in eachfield NRI=NRP*4/9.

Step 3: Calculate RI_dly as 68 mod NRI. This gives the number of the RIpackets from the beginning of the field. This number can be offset by 2to take into account the 2 robust packet delay (when TR=0, NRS=1)introduced by packet formatter 240.

Step 4: Use the value of RI_dly to determine the packet number in thefield as:init_dly=RI_delay*9*m/4.

The start signal 289 can be generated by generate start signal block 650based on this initial delay value and it can be fly-wheeled to generateit every 312 packets as long as robust de-interleaver 250 is not reset.The init_dly values can be pre-computed and stored in latency look-uptable (LUT) 640, as shown in FIG. 6. TABLE 5 shows the values forinit_dly calculated using the above algorithm for different values ofNRP, when TR=0 and NRS=1. TABLE 5 Initial Delay (“Init_Delay”) Valuesfor Different NRP Values When TR = 0 and NRS = 1 Number of Offset fromNumber of Robust Inter-robust the Field Robust Information packet sync(in Packets in Packets in spacing packets) NRP each field each field (m)RI_dly (init_dly) 0000 0 0 0 0 0 0001 9 4 4 0 0 0010 18 8 4 4 36 0011 2712 4 8 72 0100 36 16 4 4 36 0101 45 20 4 8 72 0110 54 24 4 20 180 011163 28 4 12 108 1000 72 32 4 4 36 1001 90 40 2 28 126 1010 117 52 2 16 721011 144 64 2 4 18 1100 162 72 1 68 153 1101 171 76 1 68 153 1110 216 961 68 153 1111 270 120 1 68 153

RS decoder 260 in new receiver 200 produces two output start signals forde-randomizer 270 in order to start the standard de-randomizer circuitryand the robust de-randomizer circuitry at the correct instant. RSdecoder 260 receives the data and the control signals from robustde-interleaver 250 and decodes all the packets (belonging to SS as wellas NS). RS decoder 260 generates 187 byte data packets from 207 byteinput data packets.

FIG. 7 illustrates in greater detail de-randomizer 270 of 8-VSB receiver200 according to an exemplary embodiment of the present invention.De-randomizer 270 comprises standard de-randomizer 710, robustde-randomizer 720, multiplexer (MUX) 730, look-up table (LUT) 740, andgenerate freeze signal block 750. Standard de-randomizer 710 and robustde-randomizer 720 are structurally similar standard de-randomizers.Standard de-randomizer 710 is used to de-randomize the bytescorresponding to the standard stream (SS), while robust de-randomizer720 is used to de-randomize the bytes corresponding to the new stream(NS). Standard de-randomizer 710 and robust de-randomizer 720 receivethe same data input but different start signals from RS decoder 260. Theoutput of standard de-randomizer 710 contains valid standard transportstream packets. The output of robust de-randomizer 720 contains validrobust transport stream packets. De-randomizer 270 can be programmed togive out the standard stream and/or the robust stream with NULL packetsplaced in the locations corresponding to the other stream.

De-randomizers 710 and 720 receive the error-corrected bytes from RSdecoder 260 and de-randomizes the data using a pseudo-random binarysequence (PRBS). The PRBS is generated identically to that of thetransmitter with similar feedback and output taps. The PRBS is generatedby a 16-bit shift register with the following generator polynomial:G ₍₁₆₎ =X ¹⁶ +X ¹³ +X ¹² +X ¹¹ +X ⁷ +X ⁶ +X ³ +X+1.

The shift register is initialized to F180 hex and is synchronized withthe field synchronization signal and the start signals. De-randomizers710 and 720 perform modulo-2 addition of the incoming data byte with thede-randomizer byte (formed from bits D7 to D0). De-randomizers 710 and720 operate without errors if the relative positions of the data byteshave not changed with respect to the field synchronization signal.Within a field, a data byte at a particular position in the field isalways de-randomized by the same de-randomizing byte.

The inclusion of packet formatter 240 and robust de-interleaver 250 innew dual bit-stream receiver 200 introduces a delay in the NS databytes. This delay is dependent on the parameters TR, NRS and NRP. Due tothis delay, the relative position of the NS data bytes with respect tothe field synchronization is changed. Therefore, a start signal has tobe generated indicating the location of the first RI data byte in thefield. Robust de-interleaver 250 generates this signal based on thealgorithm described above. TABLE 6 shows the location of the first RIpacket in the field for the case of TR=0 and NRS=1. The numbers in thecolumn “Offset from the Field Sync” include the 2 robust packet delayintroduced by receiver packet formatter 240. TABLE 6 Location of FirstRI Packet In a Field for Different NRP Values When TR = 0 and NRS = 1Number of Robust Packets Offset from the Field sync NRP in each field(in packets) 0000 0 0 0001 9 0 0010 18 44 0011 27 80 0100 36 44 0101 4580 0110 54 188 0111 63 116 1000 72 44 1001 90 130 1010 117 76 1011 14422 1100 162 155 1101 171 155 1110 216 155 1111 270 155

If the start signal is properly synchronized, then all the RI packetswill be de-randomized correctly as long as the inter-robust packetspacing is the same. The packet insertion mechanism in the new ATSCtransmitter does not meet this requirement for all values of NRP. Insome cases, the spacing between the last packet of a field and the firstpacket of the next field is different from the inter-robust packetspacing (usually 1, 2 or 4). TABLE 7 shows this scenario for TR=0, NRS=1and NRP=54. In this case, the inter-robust packet spacing is 4, but thespacing between the last packet of a field and the first packet of thenext field is (312−212)=100 packets. TABLE 7 Location (Field Number,Packet Number) of RI Packets in Field at De-Randomizer Input for TR = 0,NS = 1 and NRP = 54 Packet # for Robust which hd_sd = 1 packet number P,0 RN P, 4 RN P, 8 P − 1, RI 4 P, 12 RN P, 16 P − 1, RI 5 P, 20 RN P, 24P − 1, RI 6 P, 28 RN P, 32 P − 1, RI 7 P, 36 RN P, 40 RN P, 44 P − 1, RI8 P, 48 RN P, 52 P − 1, RI 9 P, 56 RN P, 60 P − 1, RI 10 P, 64 RN P, 68P − 1, RI 11 P, 72 RN P, 76 RN P, 80 P − 1, RI 12 P, 84 RN P, 88 P − 1,RI 13 P, 92 RN P, 96 P − 1, RI 14 P, 100 RN P, 104 P − 1, RI 15 P, 108RN P, 112 RN P, 116 P − 1, RI 16 P, 120 RN P, 124 P − 1, RI 17 P, 128 RNP, 132 P − 1, RI 18 P, 136 RN P, 140 P − 1, RI 19 P, 144 RN P, 148 RN P,152 P − 1, RI 20 P, 156 RN P, 160 P − 1, RI 21 P, 164 RN P, 168 P − 1,RI 22 P, 172 RN P, 176 P − 1, RI 23 P, 180 RN P, 184 RN P, 188 P, RI 0P, 192 RN P, 196 P, RI 1 P, 200 RN P, 204 P, RI 2 P, 208 RN P, 212 P, RI3 P + 1, 0 RN P + 1, 4 RN P + 1, 8 P, RI 4 P + 1, 12 RN P + 1, 16 P, RI5 P + 1, 20 RN P + 1, 24 P, RI 6 P + 1, 28 RN P + 1, 32 P, RI 7 P + 1,36 RN P + 1, 40 RN P + 1, 44 P, RI 8 P + 1, 48 RN P + 1, 52 P, RI 9 P +1, 56 RN P + 1, 60 P, RI 10 P + 1, 64 RN P + 1, 68 P, RI 11 P + 1, 72 RNP + 1, 76 RN P + 1, 80 P, RI 12 P + 1, 84 RN P + 1, 88 P, RI 13 P + 1,92 RN P + 1, 96 P, RI 14 P + 1, 100 RN P + 1, 104 P, RI 15

Consider the case of TR=0, NRS=1 and NRP=54. For this parameter set,robust de-interleaver 250 generates the start signal at packet number188. TABLE 7 shows the field number and the packet number for RIpackets. Due to the delay introduced by robust de-interleaver 250,packet RI 0 of field P appears at packet number 188 of field P. Robustde-randomizer 270 is reset at this point, so RI packets 0, 1, 2, and 3will be de-randomized correctly. However, there is a discontinuitybetween RI packets 3 and 4 since RI 3 appears in the last robust packetposition of field P and RI 4 appears in the 3^(rd) robust packetposition of field P+1. During this period, de-randomizer 270 is stillactive and so it de-randomizes RI packets following RI 3 incorrectly. Inorder to avoid this kind of scenario, de-randomizer 270 is frozen forsome duration of time by generate freeze signal processing block 750.

The duration and the position of the freeze are dependent on the TR, NRSand NRP parameters. The starting and ending positions of the freezeperiod can be determined by using the following algorithm:

Step 1: Let m be the inter-robust packet spacing corresponding to theTR, NRS and NRP parameters. The value of m is 1, 2 or 4.

Step 2: Let NRI be the number of robust information packets in eachfield NRI=NRP*4/9.

Step 3: Calculate RI_dly as 68 mod NRI. This gives the number of the RIpackets from the beginning of the field. This number can be offset by 2to take into account the 2 robust packet delay (when TR=0, NRS=1)introduced by packet formatter 240.

Step 4: Calculate ‘rem_rp’ as (NRI−RI_dly)

Step 5: If rem_rp<NRI, then go to Step 6. Otherwise, set start_count andend_count equal to 0.

Step 6: Calculate the starting point for the freeze asstart_count=(rem_rp*9/4)*m−2*m.

Step 7: Calculate the end point for the freeze asend_count=(312−NRP*4)+start_count.

The start_count and end_count values can be pre-computed and stored inlook-up table (LUT) 740. Generate freeze signal processing block 750uses these two values from LUT 740 to generate the freeze signal.Generate freeze signal processing block 750 resets a packet counter onthe start signal and increments this counter for each new packet thatthe generate freeze signal processing block 750 receives. If the packetcounter is between the ‘start_count’ and the ‘end_count’, then robustde-randomizer 270 is frozen.

Only one freeze duration is required per field for the proposed packetinsertion mechanism, but the logic can be extended to add additionalfreeze durations if required. After the freeze is released,de-randomizer 270 continues to operate until a start signal is received,at which point de-randomizer 270 is initialized. This ensures that allthe RI packets are de-randomized correctly. TABLE 8 contains the‘start_count’ and ‘end_count’ values as determined by the algorithm forthe case of TR=0 and NRS=1. TABLE 8 Start_Count and End_Count Values forDifferent NRP Values When TR = 0 and NS = 1 start_count end_count NRP(packets) (packets) 0000 0 0 0001 0 0 0010 28 268 0011 28 232 0100 100268 0101 100 232 0110 28 124 0111 136 196 1000 244 268 1001 50 182 1010158 236 1011 266 290 1100 7 157 1101 16 157 1110 61 157 1111 115 157

Standard de-randomizer 710 generates valid SS transport packets, whilerobust de-randomizer 720 generates valid NS transport packets. The twostreams can be multiplexed in different configurations depending on userpreferences. The operation of multiplexer 730 is controlled by a Selectsignal that is a combination of the hd_sd control signal, therob_pac_cnt control signal, and a user adjustable output_sw controlsignal. Multiplexer 730 adds a 3-byte NULL header to the packets whenthe control signals hd_sd and rob_pac_cnt indicates a NULL packet. Thesource decoders discard the NULL packets.

Although the present invention has been described in detail, thoseskilled in the art will understand that various changes, substitutions,variations, enhancements, nuances, gradations, lesser forms,alterations, revisions, improvements and knock-offs of the inventiondisclosed herein may be made without departing from the spirit and scopeof the invention in its broadest form.

1. A packet formatter (240) for use in a television receiver (200)capable of receiving a dual bitstream signal comprising a standardstream compatible with the Advanced Television Systems Committee (ATSC)standard and a robust stream, said packet formatter (240) comprising: afirst processing block (410) capable of receiving said dual bitstreamsignal and removing therefrom header bits and parity bits associatedwith said robust stream to thereby produce a first output signal; and asecond processing block (430) capable of receiving said first outputsignal and removing therefrom duplicate bits associated with said robuststream to thereby produce a second output signal that is output from adata path output (295) of said packet formatter (240).
 2. The packetformatter (240) as set forth in claim 1 wherein said packet formatter(240) passes bytes associated with said standard stream to said datapath output (295) of said packet formatter (240) after delaying saidstandard stream bytes by a predetermined delay time.
 3. The packetformatter (240) as set forth in claim 2 wherein said packet formatter(240) comprises a third processing block (420) capable of determiningthe locations of said parity bits in said robust stream.
 4. The packetformatter (240) as set forth in claim 3 wherein said third processingblock (420) is further capable of determining the locations of saidheader bits in said robust stream.
 5. The packet formatter (240) as setforth in claim 4 wherein said third processing block (420) comprises alook-up table (420).
 6. The packet formatter (240) as set forth in claim5 wherein said packet formatter (240) generates and outputs packetidentification information used by subsequent processing blocks (250,260, 270) following said packet formatter (240).
 7. A signal comprisingthe second output signal output from the data path output of the packetformatter (240) as set forth in claim
 1. 8. For use in a televisionreceiver (200) capable of receiving a dual bitstream signal comprising astandard stream compatible with the Advanced Television SystemsCommittee (ATSC) standard and a robust stream, a method of formattingpackets of said dual bitstream signal comprising the steps of: receivingin a packet formatter (240) said dual bitstream signal and removingtherefrom header bits and parity bits associated with said robust streamto thereby produce a first output signal; and removing from said firstoutput signal duplicate bits associated with said robust stream tothereby produce a second output signal that is output from a data pathoutput (295) of said packet formatter (240).
 9. The method as set forthin claim 8 further comprising the step of delaying bytes associated withsaid standard stream by a predetermined delay time before outputtingsaid delayed standard stream bytes on said data path output (295) ofsaid packet formatter (240).
 10. The method as set forth in claim 9further comprising the step of determining the locations of said paritybits in said robust stream.
 11. The method as set forth in claim 10further comprising the step of determining the locations of header bitsin said robust stream.
 12. The method as set forth in claim 11 whereinsaid step of determining the locations of said parity bits comprises thestep of determining the locations of said parity bits from a look-uptable (420).
 13. The method as set forth in claim 12 further comprisingthe steps of generating and outputting packet identification informationused by subsequent processing blocks (250, 260, 270) following saidpacket formatter (240).
 14. A signal comprising the second output signaloutput from the data path output of the packet formatter (240) as setforth in claim
 8. 15. A television receiver (200) comprising: receiverfront-end circuitry capable of receiving and down-converting a dualbitstream signal comprising a standard stream compatible with theAdvanced Television Systems Committee (ATSC) standard and a robuststream to thereby produce a baseband signal; and a forward errorcorrection section capable of receiving said baseband signal from saidreceiver front-end circuitry, said forward error correction sectioncomprising a packet formatter (240) comprising: a first processing block(410) capable of receiving said standard stream and said robust streamassociated with said baseband signal and removing therefrom header bitsand parity bits associated with said robust stream to thereby produce afirst output signal; and a second processing block (430) capable ofreceiving said first output signal and removing therefrom duplicate bitsassociated with said robust stream to thereby produce a second outputsignal that is output from a data path output (295) of said packetformatter (240).
 16. The television receiver (200) as set forth in claim15 wherein said packet formatter (240) passes bytes associated with saidstandard stream to said data path output (295) of said packet formatter(240) after delaying said standard stream bytes by a predetermined delaytime.
 17. The television receiver (200) as set forth in claim 16 whereinsaid packet formatter (240) comprises a third processing block (420)capable of determining the locations of said parity bits in said robuststream.
 18. The television receiver (200) as set forth in claim 17wherein said third processing block (420) is further capable ofdetermining the locations of said header bits in said robust stream. 19.The television receiver (200) as set forth in claim 18 wherein saidthird processing block (420) comprises a look-up table (420).
 20. Thetelevision receiver (200) as set forth in claim 19 wherein said packetformatter (240) generates and outputs packet identification informationused by subsequent processing blocks (250, 260, 270) following saidpacket formatter (240).
 21. A data de-randomizer (270) for use in atelevision receiver (200) capable of receiving a dual bitstream signalcomprising a standard stream compatible with the Advanced TelevisionSystems Committee (ATSC) standard and a robust stream, said datade-randomizer (270) comprising: a standard de-randomizer (710) capableof de-randomizing bytes associated with said standard stream; and arobust de-randomizer (720) capable of de-randomizing bytes associatedwith said robust stream.
 22. The data de-randomizer (270) as set forthin claim 21 wherein said data de-randomizer (270) further comprises adelay calculation circuit (740,750) for determining a delay with respectto a field synchronization signal associated with the robust stream.